1. Field of the Invention
The present invention relates to an electronic circuit and an integrated circuit including a scan testing circuit, and a power consumption reducing method used for the integrated circuit and, in particular, to an electronic circuit and an integrated circuit including a scan testing circuit that are capable of reducing power consumption in normal operation mode other than in scan testing mode, and a power consumption reducing method used for the integrated circuit.
2. Description of the Related Art
LSIs (Large Sale Integrated circuits) comprising multiple flip-flops (FFs) also have an embedded circuit for a scan being carried out as an operation test of the LSIs at manufacturing time. These LSIs are called scan-testable integrated circuits. In scan-based testing, each of the FFs of the LSI enters scan test mode in which the FFs are chained together into a shift register called a scan chain. A test input signal is input to the first-stage FF of the scan chain and a test result signal is output from the last-stage FF. The test result signal output from the last-stage FF is compared with a predetermined expected signal in a scan test device. If they do not match, some of the FFs scan-tested supposed to be faulty and the LSIs should be rejected.
FIGS. 3A to 3C show such a conventional LSI for example. The LSI in these figures has a p-channel MOSFET (Metal Oxide-Semiconductor Field-Effect Transistor, herein after referred to as a “pMOS”) 1, an n-channel MOSFET (hereinafter referred to as an “nMOS”) 2, a pMOS 3, an nMOS 4, a pMOS 5, an nMOS 6, inverters 7 and 8, a pMOS 9, an nMOS 10, a pMOS 11, an nMOS 12, inverters 13 and 14, a pMOS 15, an nMOS 16, and inverters 17 and 18 as shown in FIG. 3A, and inverters 19 and 20 shown in FIG. 3B, and inverters 21 and 22 shown in FIG. 3C. These elements constitute a scan FF. The whole LSI includes a plurality of FFs, not shown, similar to the scan FFs described above. As shown in the table in FIG. 3D, the LSI enters scan test mode when “1” is input as a mode setting signal (SCANMODE) which is input in SCANMODE terminal shown in FIG. 3C. FIG. 4 shows an operation of the conventional circuit shown in FIG. 3A to 3C. As shown in FIGS. 3D and 4, a scan output signal SCNOutPin (SOUTB) alternately changes in accordance with an input signal. When another mode setting signal (SCANMODE) “0” is input, the LSI switches to normal operation mode. Also in normal operation mode, the scan output signal SOUTB alternately changes in accordance with an input signal, same as in scan test mode.
Referring to FIGS. 3A to 3C, the operation will be described in detail. When the mode setting signal SCNMODE “1” is input, the LSI enters scan test mode. Because input to SCANMODE is “1”, a control signal SMCB becomes “0” and another control signal SMCT becomes “1” in the circuit shown in FIG. 3C. As a result, the pMOS 1 and nMOS 2 in the circuit shown in FIG. 3A turn on and the pMOS 3 and nMOS 4 turn off. Since the pMOS 3 and nMOS 4 turn off, a DATA signal is not input in the pMOS 5 and nMOS 6. On the other hand, because the pMOS 1 and nMOS 2 turn on, a SCANDATA signal output from the preceding FF, not shown, is input in pMOS 5 and nMOS 6. The pMOS 5 and nMOS 6 turn on at the trailing edge of a clock CLK and the SCANDATA signal is input in the inverter 7.
At the leading edge of the clock CLK, the pMOS 5 and nMOS 6 turn off and the pMOS 9 and nMOS 10 turn on, and thus a master latch composed of inverters 7 and 8 holds the SCANDATA signal. Since pMOS 11 and nMOS 12 are in the on state, the held SCANDATA is input in the inverter 13 and is also output as a normal operation output signal Q to the outside through the inverter 18. At the trailing edge of the clock CLK, the pMOS 11 and nMOS 12 turn off and the pMOS 15 and nMOS 16 turn on, and thus a slave latch composed of the inverters 13 and 14 holds the SCANDATA. The held SCANDATA is output as a scan output signal SOUTB through the inverter 17 and is provided to the subsequent FF, not shown.
When “0” is input in SCANMODE, the LSI enters normal operation mode. Since the input into SCANMODE is “0”, the control signal SMCB in the circuit shown FIG. 3C becomes “1” and the control signal SMCT becomes “0”. As a result, the pMOS 1 and nMOS 2 in the circuit shown in FIG. 3A turn off and the pMOS3 and nMOS 4 turn on. Since the pMOS 3 and nMOS 4 are on, the normal operation data “DATA” is input in the subsequent-stage circuit through the pMOS 3 and nMOS4. Thus, the DATA signal is input in place of the SCANDATA signal and subsequently the LSI operates as in scan test mode.
There is a strong demand for reduction of power consumption in LSIs in these years. However, there is a problem with LSIs including a scan testing circuit that the scan testing circuit also operates during normal operation and thus wastes power. More specifically, the scan output signal SOUTB for example is output from the inverter 17 in the LSI described above and shown in FIG. 3A to 3C in normal operation mode as well and therefore power is wasted. To solve the problem, LSIs that deactivate hardware components that are not needed in normal operation mode have been proposed.
For example, there are techniques described in the following documents.
Japanese Patent Laid-Open No. 2001-201542 proposes a technique for reducing power consumption in a scan flip-flop circuit. FIG. 5 shows FIG. 1 of Japanese Patent Laid-Open No. 2001-201542. In the scan flip-flop described in Japanese Patent Laid-Open No. 2001-201542, when an active mode “1” is input as a test enable signal to the circuit shown in FIG. 5 and the circuit enters in scan test mode, a NAND circuit outputs a scan output signal that depends on an input signal. When a non-active mode “0” is input as the test enable signal to the circuit and the circuit enters in normal operation mode, the scan output signal is fixed to “1” regardless of an input signal. Thus, power consumption brought by variations of the scan output signal in normal operation is reduced.
National Publication of International Patent Application No. 2004-536487, which is the published Japanese translation of PCT international publication for International Publication No. WO2002/080368, proposes a technique for reducing power consumption in a buffer circuit. FIGS. 6A and 6B show FIG. 4 of the National Publication of International Patent Application No. 2004-536487. The buffer circuit described in National Publication of International Patent Application No. 2004-536487 has first and second inverters interconnected in series. A pMOS transistor is connected between the first inverter and a power supply potential and an nMOS transistor is connected between the second inverter and a ground potential. The pMos and the nMOS transistors are turned on through a memory cell when the buffer circuit is in use. When the buffer circuit is not in use, they are turned off through the memory cell.
However, these conventional techniques have the following problems.
The technique described in Japanese Patent Laid-Open No. 2001-201542 requires a full-set NAND gate which fixes the scan output signal. Power consumption for driving a full-set gate scale circuit is not small. A NAND gate also consumes not small power and requires current for driving such as operation current and standby current.
The buffer circuit described in National Publication of International Patent Application No. 2004-536487 is intended for reduction of leakage current in a static CMOS circuit. Transistors are added to the buffer circuit and are controlled by using a memory cell. That is, the technique described in National Publication of International Patent Application No. 2004-536487 suites in the buffer circuit because it requires a memory cell. Because of the same reason, the technique does not suite for reducing power consumption of flip-flop with scan testing circuit.
The present invention has been made in view of these circumstances and an object of the present invention is to provide an electronic circuit and an integrated circuit including a scan testing circuit that reduce power consumption in normal operation mode and a power consumption reducing method used for the integrated circuit.